1. Field of the Invention
The present invention relates to a semiconductor memory device which has a plurality of operation modes and can reduce a consumed electric current by carrying out the switching control of internal signals required for the respective operation modes by required minimum control, a control method thereof, and a control method of a semiconductor device.
2. Description of Related Art
Conventionally, irrespective of synchronous type/asynchronous type, a semiconductor memory for memorizing data by storing an electric charge in a cell capacitor, such as a dynamic random access memory (hereinafter abbreviated to a DRAM), has a refresh operation mode in addition to an ordinary data-input/output operation mode. These operations have, as one unit, a so-called operation cycle in which on the basis of an external command etc., an access operation to a memory cell, such as an input/output operation of data or a refresh operation, is carried out from a stand-by state, and is again returned to the stand-by state. Setting of the operation mode has been carried out for every operation cycle to determine what access operation is to be carried out in each of the operation cycles.
In the refresh mode, it is necessary to repeatedly refresh all memory cells in the DRAM successively within a predetermined time. Then, it is common to continuously carry out the refresh operation in a period when the ordinary data-input/output mode is not in action. By a so-called self-refresh mode, in each cycle from the entry of a self-refresh command to the exit in the synchronous type DRAM, or in the set period of CAS before RAS in the asynchronous type DRAM, the refresh operation is successively carried out for the respective memory cells while an internal address is switched. Since the operation mode is fixed to the refresh mode in this period, the operation mode for each operation cycle is not confirmed, and direct transition of the address of the memory cell as an object to be refreshed is carried out without going through an intermediate state such as a reset of address content outputted from the internal address between the operation cycles.
In recent years, with the spread of portable equipment, the functions demanded for the equipment are increased, and consequently, instead of a conventionally mounted static random access memory (hereinafter abbreviated to an SRAM), a memory of further large capacity has been demanded. Then, a DRAM having a built-in refresh function, a so-called pseudo-SRAM has been used, which uses a highly integrated DRAM memory cell as compared with an SRAM memory cell and has a built-in control concerning the refresh operation peculiar to the DRAM memory cell, so that an external control circuit such as a refresh controller is made unnecessary and the external specification is equivalent to the SRAM.
The pseudo-SRAM is automatically shifted to the refresh mode at any time as the need arises, and can carry out the refresh operation. Thus, in both the refresh mode of the internal control and the ordinary data-input/output mode of the external control, the operation requests are made at arbitrary timings, and synchronization can not be established between both the operation modes. Accordingly, the pseudo-SRAM cannot adopt the continuous refresh operation in which the direct transition of the inner address is carried out without confirming the operation mode for each operation cycle, and differently from the normal DRAM, it is necessary to discriminate the operation mode for each operation cycle. Thus, it is necessary to switch the state of the internal address into a specified state for each operation cycle.
Specifically, for example, in the case where the ordinary data-input/output mode of the external control is set as the basic operation mode, each time the operation cycle of the refresh mode is ended, the setting of the internal address is switched to the external address required in the ordinary data-input/output mode. Besides, if such an architecture is adopted that an intermediate reset state is set between operation cycles, the internal address is switched to the reset state each time the operation cycle of the refresh mode is ended.
FIG. 15 shows operational waveforms expressing address switching for each operation cycle concerning the pseudo-SRAM in which the ordinary data-input/output mode is set as the basic operation mode. A period in which a refresh operation requesting signal REQ (Ref) is selected is an operation period Ref of a refresh mode, and a refresh address ADD (Ref) generated in an internal address counter or the like is propagated to an internal address ADD (Int). Besides, a period in which a data-input/output requesting signal REQ (R/W) is selected, is an operation period R/W of a data input/output mode in which read/write of data is carried out, and an external address ADD (R/W) inputted from the outside is propagated to the internal address ADD (Int).
Besides, in the operation periods Ref and R/W of the refresh mode and the ordinary data-input/output mode respectively, it is necessary to select a memory cell block as a unit of memory cell activation. Since the memory cells are arranged in a matrix form, as signals for selecting the memory cell block, the signals for selecting the respective directions of a row direction and a column direction are needed. One signal of those is a block selecting signal CBx (x=0 to n). The number of the memory cell blocks selected by this signal CBx (x=0 to n) becomes a less selection number at the time of the ordinary data-input/output mode in which the input/output of data from/to the outside exists and it is desired to perform an operation at a required minimum consumed electric current, as compared with the time of the refresh mode in which a refresh period is regulated from the data holding characteristic. In FIG. 15, at the time of the ordinary data-input/output mode, one block selecting signal CBa or CBb is activated. On the other hand, at the time of the refresh mode, all the block selecting signals CBx (x=0 to n) are activated.
In FIG. 15, since the ordinary data-input/output mode is made the basic operation mode, at the time of the end of the operation period Ref of the refresh mode, the settings of the internal address ADD (Int) and the cell block selecting signal CBx (x=0 to n) become the external address ADD (R/W) of the ordinary data-input/output mode and the cell block selecting signal CBa or CBb.
In the above, the pseudo-SRAM is used as an example, and the description has been given of, as an example, the case where the address is switched between the internal address and the external address for each of two different operation modes of the refresh mode of the internal control and the data-input/output mode of the external control. Also in other semiconductor devices, there is a case where switching of an internal state typified by address switching at every operation mode is carried out.
However, in the conventional pseudo-SRAM, even if a next operation cycle subsequent to the refresh mode is the ordinary data-input/output mode, as the internal address ADD (Int) in the stand-by period SBY between these, as indicated by a region (A) of FIG. 15, there is a fear that an address value (B1 or B2) of an unnecessary external address ADD (R/W) is set. At this time, the switching operation from the address value (A1 or A4) of the refresh address ADD (Ref) to the unnecessary address value (B1 or B2), and the switching operation from the unnecessary address value (B1 or B2) to the address value (B2 or B3) at the time of the ordinary data-input/output mode are unnecessary operations, and unnecessary electric current consumption is caused, which is problematic.
Such connection switching to the internal address ADD (Int) arises also in an operation state like a region (B) of FIG. 15 in which the refresh mode continues over a plurality of operation cycles. In this case, since the operation of the refresh mode continues as the operation in the pseudo-SRAM, the address value required as the internal address ADD (Int) is the address values A2 to A4 from the refresh address ADD (Ref). However, in the stand-by period SBY of the refresh mode, the address is switched to the address value B2 from the external address ADD (R/W), and the consumed electric current by the unnecessary operation resulting from this flows, which is problematic.
The invention has been made to solve the problems of the background art, and has an object to provide a semiconductor memory device which has a plurality of operation modes and can reduce a consumed electric current by carrying out the switching control of internal signals required for the respective operation modes by required minimum control, a control method thereof, and a control method of a semiconductor device.
In order to achieve the above object, a semiconductor memory device according to one aspect of the invention is a semiconductor memory device in which internal states at a time of carrying out an access operation to a memory cell have two or more different operation modes, and comprises a mode discriminating section for discriminating one of the operation modes at every operation cycle constituted by, as one unit, an operation period for carrying out the access operation and a stand-by period from an end of the operation period to a start of a next operation period, a switching section for switching among the internal states, and a switching control section for outputting a switching control signal to the switching section in accordance with a discrimination result obtained in the mode discriminating section, in which the switching control signal is not outputted in the stand-by period before a start of the operation cycle, but is outputted in the operation period subsequent to the start of the operation cycle.
In the semiconductor memory device, the mode discriminating section discriminates one of the operation modes in the operation cycle, and the switching control section outputs the switching control signal to the switching section for switching among the internal states in accordance with the discrimination result of the mode discriminating section. At this time, the switching control signal is not outputted in the stand-by period before the start of the operation cycle, but is outputted in the operation period subsequent to the start of the operation cycle.
By this, in accordance with the discrimination result of the operation mode, the switching control signal is outputted not in the stand-by period before the start of the operation cycle, but in the operation period subsequent to the start of the operation cycle, so that there does not occur such a state that the switching control signal is outputted before the operation cycle, and the switching control signal is further switched at the time of the start of the subsequent operation cycle or at the timing thereafter, and a suitable switching control signal is outputted at a suitable timing in accordance with the discrimination result. The output of an unnecessary switching control signal, switching of the signal, or the like is not caused, the switching section can be controlled by the output of the required minimum switching control signal, and the electric current consumption resulting from the signal switching can be suppressed to be minimum.
Besides, a semiconductor memory device according to another aspect of the invention is a semiconductor memory device having a data-input/output mode and a refresh mode as an access operation to a memory cell, and comprises a mode discriminating circuit for discriminating between the data-input/output mode and the refresh mode at every operation cycle constituted by, as one unit, an operation period for carrying out the access operation and a stand-by period from an end of the operation period to a start of a next operation period, a switching control circuit for outputting a switching control signal in the operation period after a start of the operation cycle only in a case where an operation mode discriminated by the mode discriminating circuit is different from an operation mode in the former operation cycle, and an address switching circuit for switching connection to a decoding circuit at every output of the switching control signal, while one of an external address used in the data-input/output mode and a refresh address used in the refresh mode from a refresh address counter is always connected to the decoding circuit.
In the semiconductor memory device, the mode discriminating circuit discriminates one of the operation modes in the operation cycle, and in accordance with the discrimination result of the mode discriminating circuit, the switching control circuit renews the switching control signal. The address switching circuit receiving the switching control signal connects either one of the external address or the refresh address to the decoding circuit. The switching control signal is not renewed in the stand-by period before the start of the operation cycle, but is renewed in the operation period subsequent to the start of the operation cycle.
Besides, a semiconductor memory device according to a third aspect of the invention is a semiconductor memory device having a data-input/output mode and a refresh mode as an access operation to a memory cell, and comprises a mode discriminating circuit for discriminating between the data-input/output mode and the refresh mode at every operation cycle constituted by, as one unit, an operation period for carrying out the access operation and a stand-by period from an end of the operation period to a start of a next operation period, a switching control circuit for outputting a switching control signal in the operation period after a start of the operation cycle only in a case where the operation mode discriminated by the mode discriminating circuit is different from the operation mode in the former operation cycle, and a block decoding circuit in which, when a memory cell array block to be accessed is specified, either a first number of bits with respect to address decoded in the data-input/output mode or a second number of bits with respect to address decoded in the refresh mode, smaller than the first number of bits, is always connected, and connection is switched at every output of the switching control signal alternately between the first number and the second number.
In the semiconductor memory device, the mode discriminating circuit discriminates one of the operation modes in the operation cycle, and in accordance with the discrimination result of the mode discriminating circuit, the switching control circuit renews the switching control signal. The block decoding circuit receiving the switching control signal switches and connects either one of the first bit number or the second bit number. The switching control signal is not renewed in the stand-by period before the start of the operation cycle, but is renewed in the operation period subsequent to the start of the operation cycle.
By this, in accordance with the discrimination result of the operation mode, the switching control signal selecting either one of address supply paths or either one of the numbers of bits with respect to address for selecting activating sections of a memory cell array is renewed not in the stand-by period before the start of the operation cycle, but in the operation period after the start of the operation cycle, so that there does not occur such a state that the switching control signal is outputted before the operation cycle, and the switching control signal is further switched at the time of the start of the subsequent operation cycle or at the timing thereafter, and a suitable switching control signal is outputted at a suitable timing in accordance with the discrimination result. The output of an unnecessary switching control signal, switching of the signal, or the like is not caused, the switching section can be controlled by the output of the required minimum switching control signal, and the electric current consumption resulting from the signal switching can be suppressed to be minimum.
Besides, a control method of a semiconductor memory device according to one aspect of the invention is a control method of a semiconductor memory device in which address supply paths at a time of carrying out an access operation to a memory cell have two or more different operation modes, and comprises a mode discriminating process of discriminating one of the operation modes at every operation cycle constituted by, as one unit, an operation period for carrying out the access operation and a stand-by period from an end of the operation period to a start of a next operation period, and a switching control process of renewing a switching control signal selecting one of the address supply paths in accordance with a discrimination result of the mode discriminating process, not in a stand-by period before a start of the operation cycle, but in an operation period subsequent to the start of the operation cycle.
In the control method of the semiconductor memory device, the operation mode in the operation cycle is discriminated in the mode discriminating process, and the switching control signal selecting one of the address supply paths is renewed in the switching control process in accordance with the discrimination result of the mode discriminating process. At this time, the switching control signal is not renewed in the stand-by period before the start of the operation cycle, but is renewed in the operation period subsequent to the start of the operation cycle.
Besides, a control method of a semiconductor memory device according to another aspect of the invention is a control method of a semiconductor memory device in which activating sections of a memory cell array at a time of carrying out an access operation to a memory cell have two or more different operation modes, and comprises a mode discriminating process of discriminating one of the operation modes at every operation cycle constituted by, as one unit, an operation period for carrying out the access operation and a stand-by period from an end of the operation period to a start of a next operation period, and a switching control process of renewing a switching control signal selecting one of bit numbers of address of the activating sections in accordance with a discrimination result of the mode discriminating process, not in a stand-by period before a start of the operation cycle, but in the operation period subsequent to the start of the operation cycle.
In the control method of the semiconductor memory device, the operation mode in the operation cycle is discriminated in the mode discriminating process, and in accordance with the discrimination result of the mode discriminating process, the switching control signal selecting one of address bit numbers of the activating sections of the memory cell array is renewed in the switching control process. At this time, the switching control signal is not renewed in the stand-by period before the start of the operation cycle, but is renewed in the operation period subsequent to the start of the operation cycle.
By this, in accordance with the discrimination result of the operation mode, the switching control signal selecting one of the address supply parts or one of the bit numbers of the address for selecting the activating sections of the memory cell array is renewed not in the stand-by period before the start of the operation cycle, but in the operation period subsequent to the start of the operation cycle, so that there does not occur such a state that the switching control signal is outputted before the operation cycle, and the switching control signal is further switched at the time of the start of the subsequent operation cycle or at the timing thereafter, and a suitable switching control signal is outputted at a suitable timing in accordance with the discrimination result. The output of an unnecessary switching control signal, switching of the signal, or the like is not caused, the switching section can be controlled by the output of the required minimum switching control signal, and the electric current consumption resulting from the signal switching can be suppressed to be minimum.
Besides, a control method according to one aspect of the invention in which internal states at a time of carrying out an activating operation have two or more operation modes, comprises a mode discriminating process of discriminating one of the operation modes at every operation cycle constituted by, as one unit, an operation period for carrying out the activating operation and a stand-by period from an end of the operation period to a start of a next operation period, a mode recording process of storing one of the operation modes discriminated in the mode discriminating process, a comparison process of comparing one of the operation modes discriminated in the mode discriminating process with one of the operation modes of the former operation cycle stored in the mode recording process, and a switching control process of giving a switching-procedure instruction among the internal states in accordance with the comparison result in the comparison process, not in the stand-by period before a start of the operation cycle, but in the operation period subsequent to the start of the operation cycle.
In the control method, the operation mode of the operation cycle is discriminated in the mode discriminating process, the operation mode discriminated in the mode discriminating process is compared with the operation mode of the former operation cycle stored in the mode recording process, and the switching-procedure instruction among the internal states is given in accordance with the comparison result. This instruction is not given in the stand-by period before the start of the operation cycle, but in the operation period subsequent to the start of the operation cycle.
By this, in accordance with the discrimination result of the operation mode, the switching-procedure instruction among the internal states is given not in the stand-by period before the start of the operation cycle, but in the operation period after the start of the operation cycle, so that there does not occur such a state that the switching-procedure instruction is given before the operation cycle, and the switching-procedure instruction is further switched at the time of the start of the subsequent operation cycle or at the timing thereafter, and a suitable instruction is carried out in accordance with the discrimination result. There does not occur an unnecessary switching-procedure instruction, the switching selecting one of the internal states can be controlled by the required minimum instruction, and the electric current consumption resulting from the signal switching can be suppressed to be minimum.
The above and further objects and novel features of the invention will more fully appear from the following detailed description when the same is read in connection with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention.